A system-on-a chip (SoC) may contain core circuits that operate at a lower supply voltage than interface circuits used to drive off-chip circuits. For example, core circuits may operate at a power supply voltage of 1 V in order to take advantage of space efficient transistors that are implemented using state of the art fine geometry processes. On the other hand, interface circuits may operate at a power supply voltage of 3.3 V or higher in order to comply with interface requirements of off chip circuits. Consequently, these interface circuits may use less space efficient transistors that are capable of operating at higher voltages. By partitioning core circuits and interface circuits to use different device geometries in different voltage domains, the size and power consumption of an integrated circuit can be optimized.
In order to provide an interface between low and high voltage domains, the SoC may use level shifting circuits to transfer data between these domains. For example, a low-to-high level shifter may be used to propagate a digital signal between a low voltage domain and a high voltage domain, and are commonly implemented using cross-coupled positive feedback circuits. Such level shifters that use high voltage devices, however, may dissipate higher transient power consumption and propagation delay than regular logic devices. Furthermore, the performance of level shifting circuits, including speed and power consumption may vary over process, temperature, and power supply voltage. In some cases, this propagation delay and power consumption may be a limiting performance factor in a SoC.